A Ka-band Two-way Combined Power Amplifier in 65-nm CMOS Technology

A fully integrated two-way differential power amplifier with two stages is designed and simulated in 65-nm CMOS technology. The circuit uses parallel power combination and stacked transistor techniques with neutral capacitors to improve high frequency gain and circuit stability. The driver stage applies a common-source architecture while the amplifier stage applies a common-source common-gate architecture (cascode), both of which are biased in Class AB. The power amplifier achieves a saturated output power of 23.2 dBm and a maximum peak efficiency of 26.6% at 30 GHz. The saturated output power is more than 20 dBm over the frequency band of 25 GHz to 35 GHz.