Test Pattern Generation in BIST Architecture Using One-Hot Encoding

As recent VLSI design and packaging processes develop, testing an IC externally using Automatic Test Equipment (ATE) becomes more complicated. A technique for adding extra software as well as hardware features to integrated circuits in order to enable self-testing is known as BIST, or Built-in selftest. TPC entails the employment of strategies to reduce the number of test vectors, hence reducing testing time and resources. This work develops a BIST Architecture with a Test Pattern Generator (TPG) that uses the One Hot Encoding technique in TPC approach. The proposed architecture was developed in Verilog and implemented in Xilinx ISE, which was synthesized in Cadence Genus at 45nm technology. The simulation results show 9.769%, 2.908%, 6.646%, and 2.059% decrease in leakage power, total power, area, and delay respectively, while using the proposed One-Hot Encoding TPG.