Automatic Creation of TVS SPICE Models for ESD System Level Simulations

The development and implementation of an algorithm for the automatic generation of a complete system-efficient ESD design (SEED) model for transient voltage suppressors (TVS), is presented. The algorithm uses transmission line pulse measurement data and S-parameter measurements to compute values for a small-signal model, IV curve model, and transient model. These models are combined into a single schematic to simulate the complete behavior of the device under test (DUT). The algorithm is constrained to TVS diodes without snapback and varistors, the resulting model matches the measured device behavior with high accuracy.