Voltage Offset Compensation in CMOS OTAs: Novel Approaches for Temperature Drift Improvement

This invited paper introduces novel approaches for trimming the voltage offset of CMOS operational amplifiers and comparators. The presented methods can be applied either to a one-time trimming during production testing, or via periodic calibration during circuit operation. The primary focus of this paper is to optimize the temperature drift of the trimmed and untrimmed offset voltage, V
OS
. The paper discusses various approaches to achieve this goal, including a) constant current injection, b) MOS physical size programming, and c) tail offset voltage trimming. Furthermore, the paper introduces new techniques that enhance temperature drift performance: d) temperature compensated current offset injection, e) temperature compensated active load trimming, f) constant-resistance tail offset voltage trimming, and g) series input-referred voltage generator. Additionally, the paper introduces the concept of transconductance temperature characteristic dumping, which has the potential to improve the residual temperature drift of the OTA. Simulation in 130nm CMOS demonstrating the effectiveness of the presented methods are provided.