Static and Dynamic Key Error Modeling for High-Speed Segmented Current Steering Digital-to-Analog Converter

High-speed and high-precision digital-to-analog converter (DAC) has significant application value in various fields, including communication, test and measurement instruments and radar. The segmented current steering DAC has gained widespread attention due to its high-speed and high-precision characteristics. However, the current fabrication processes still have room for improvement in terms of the spurious-free dynamic range and other characteristics of the DAC. In order to address this, this article introduces a modeling method for the error model of the segmented current steering DAC. Three models are developed in this study, which include the ideal segmented current steering DAC model, the current source mismatch error model, and the finite output impedance error model. Additionally, a novel method using RC filtering is introduced to model the clock feedthrough error for the first time. The proposed models are further analyzed to examine their effectiveness and accuracy in capturing the static and dynamic characteristics.