Method for Delay Recovery of Trigger Signals

This article presents a method of utilizing the SPARTAN-6 series Field-Programmable Gate Array (FPGA) to precisely measure the arrival time of trigger signals and subsequently recover them based on a predefined delay. In various nodes of the accelerator, it's necessary to delay the output of received trigger signals. To obtain an accurate recovery signal, we employ the carry chain within the FPGA to precisely measure the arrival time of the trigger signals. Simultaneously, we use the carry chain to accurately control the output delay. Ultimately, we generate a recovery signal with a time resolution of less than 120 ps.