Low Power Performance Analysis of 16-Bit Vedic Math RISC Processor

The aim of the paper is to design a low-power 16-Bit Reduced Instruction Set Computer (RISC) processor. The processer design with Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Math Sutra. The Vedic Math Sutras lies in their ability to simplify and speed up mathematical calculations. These sutras provide a systematic approach to problem-solving to solve mathematical problems quickly and accurately. Within the 16 sutras Urdhva-Triyagbhyam is one among them which means “vertically and crosswise calculations. Introducing Urdhva-Triyagbhyam Vedic Math Sutra in a 16-Bit RISC processor allows to achieve fast operation with less instruction set. This sutra can be implemented using a sequence of simple instructions to perform the multiplication operation. Therefore, the multipliers and adders are designed using Verilog Hardware Descriptive Language (HDL) and simulated through XILINX Vivado software with Artix 7 board. The work uses three Ripple Carry Adder (RCA) and one half-adder of 16 Bit in multiplier unit to reduce power consumption, delay and Slice/Look Up Table (LUT). In addition, modules like Program Counter, Register Bank and Memory block units are designed within RISC Processor. The proposed architecture emphasizes the utilization of LUT's are 997 through which the power consumption is reduced to 0.18W. Hence the speed of operation, reduction in power consumption, and area are improved