A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS

This paper describes a coherent UWB receiver architecture based on a quadrature hybrid correlation (QHC) method to significantly reduce the digital correlation power of the conventional standard-compliant UWB receiver. The proposed QHC receiver front end employs analog correlation, two-step synchronization, and time-interleaved (TI) sampling methods for low-power synchronization and demodulation. A code-mismatchevaluation method is introduced for localization, and a ternary analog correlator is proposed for noise mitigation and high-quality computing. The receiver supports preamble, scrambled timestamp sequence (STS) and burst position modulation (BPM). The proposed 8GHz receiver implemented in 65nm CMOS consumes 17. 3mW at 0. 98Mbaud/s with a sensitivity of -88dBm at a BER of 10-3 and -24dBm blocker tolerance, enabling the lowest baseband power among standard-compliant UWB receivers. In the STS field, the receiver achieves an RMS ranging error of 1. 9cm.