An Efficient Full Adder by Investigating XOR and XNOR Logics with PMOS and NMOS

Investigating the XOR and XNOR logics allows for the establishment of a fast adder in the context of CMOS. The supreme aspiration of the work is to disrate the power consumption and power dissipation as well as curtailment the size of the full adder. The suggested work is intended with 10 transistors with CMOS logic and K-mapping for logic abbreviation. The system has achieved 62.77% in diminishing the power consumption, 68.134% in the crispness of the size of the full adder, and 44.11% in lessening the power dissipated. The proposed work is prosecuted in various CMOS technologies and assimilated with the conventional 10 T full adder. It is investigated that the proposed work has a sharpened performance.