Binary-weighted Modular Multi-level Digital Active Gate Driver

This paper proposes a modular multi-level digital active gate driver topology consisting of several sub-modules with binary-weighted voltages. It can coordinate both the dynamic and the static behavior of SiC MOSFETs by shaping the gate voltage waveform using 15 voltage levels, which is particularly beneficial in parallel operation of the power devices. It is verified that the proposed gate driver can improve the current-sharing performance of parallel-connected SiC MOSFETs under several usually-undesired conditions with mismatched parameters.