Power Control and Voltage Balancing Strategies for a Five-Level T-Type Inverter

This paper presents the performance of a grid-tied five-level inverter (T5). Its structure requires fewer power components than the Neutral Point Clamped (NPC) and Flying Capacitor (FC) structures with equivalent voltage levels. The objective is to evaluate the PI, LMI (Linear Matrix Inequality) and SM (Sliding Mode) controllers for d- and q-axis current reference tracking. Each of these controllers is associated with a Space Vector Modulation technique (SVPWM) that provides DC-side capacitor voltage balancing. Efficiency and size are optimized as no additional components are required. The simulation of the complete system is performed on MATLAB/Simulink.