Systematic Derivation and Experimental Verification of a Compact Loss Model for Soft-switching Half-bridges

Soft-switching Half-Bridges (HBs) experience switching losses, even under zero-voltage-switching (ZVS) conditions, due to hysteresis losses during the charging and discharging of the output capacitor in the switching devices. This paper presents a systematic derivation and experimental verification of a compact loss model that incorporates hysteresis losses for soft-switching HBs. The model is generated by extracting parasitics, including measuring hysteresis losses using the Sawyer-Tower Method (STM). The hysteresis losses are modeled as losses occurring on an equivalent resistor connected in series with the output capacitor. Measurement results indicate that at test frequencies above 10 MHz, hysteresis losses can account for over 30% of the energy stored in the output capacitor for tested low-voltage Si MOSFETs. This finding demonstrates the significant impact of hysteresis losses on damping effects following switching events. The proposed model is verified through the Double Pulse Test (DPT), with a prediction error of switching-off losses below 10% under different operating conditions.