A hardware acceleration architecture design for histogram equalization with locking features

Histogram equalization has been widely used in image processing, which can significantly improve image contrast and enhance the effect of display. In many imaging fields, such as handheld imaging, to achieve real-time imaging function, many FPGA-based hardware acceleration designs for histogram equalization have been proposed. However, all of the aforementioned studies employ methods for real-time histogram calculation and update, which cannot be applied to dynamic imaging applications with occlusion, overexposure, and other factors in some areas. In this paper, a histogram equalization hardware acceleration structure design with locking features is proposed, which can effectively solve the above problems. In this paper, the architecture design of hardware acceleration is first proposed, including the histogram statistics module, the histogram locking and selection module, the histogram equalization calculation module, and other core circuit modules. Then, calculation accuracy tests were conducted on each logic circuit module. Finally, the overall performance of the system was tested using a publicly available vascular imaging dataset. The experimental results show that this design can avoid computational errors in dynamic imaging applications compared with existing hardware acceleration schemes. This design can be widely applied in dynamic imaging, industrial monitoring, and other related application scenarios, promoting the development of real-time imaging technology.