Energy and Computing Assessment of Video Processing Kernels on CPU and FPGA platforms

Heterogeneous architectures are becoming increasingly common, allowing the acceleration of smaller modules that compose complex systems. This is specially beneficial when said systems contain mixed data-flow and control-flow algorithms, in which the former can be hardware-optimized whereas the latter can still execute in a CPU. In video encoders, the intra- and inter-prediction are typical examples of data-flow operations. These steps involve block-matching searches that aim at finding the most similar pair of blocks, one being encoded and one that is generated during prediction. The similarity can be measured in different ways, but the most common ones are the Sum of Absolute Differences (SAD), the Sum of Absolute Transformed Differences (SATD), and the Sum of Squared Differences (SSD). All of these distortion metrics are executed several times for each block being encoded, so reducing the time or energy required to compute them is extremely beneficial. This paper presents a comparison of the energy costs of the SAD and SSD operations on a CPU and on dedicated VLSI designs. The experiments were conducted in an Artix-7 based FPGA component. The VLSI architectures and simulation routines were designed with VHDL, and the software versions were described in C. To optimize throughput and resource utilization, the dedicated units were designed using pipeline and resource sharing when possible. Our results show that, as expected, FPGA has a great gain of energy efficiency over CPU, with power efficiency gains in the range of 100 times.