Memory Controller with Adaptive ECC for Reliable System Operation

Memory errors can cause crashes and data loss, which are unacceptable for various computing systems, mainly large servers. Memory controllers can mitigate these errors by employing an Error Correction Code (ECC) in the data write and read flows. This work proposes a fault-tolerant mechanism that acts as a memory controller's encoding and decoding manager. This mechanism adapts the ECC for each memory block based on the efficacies of the ECCs available in the controller and the error rate captured at runtime. Consequently, memory blocks with a high error rate can be recoded to a high efficacy ECC and vice versa. Experimental results show that our proposal achieves high error correction efficacy with high energy efficiency.