Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FME

The Versatile Video Coding (VVC) standard incorporates a number of new tools to significantly improve the coding efficiency over its predecessor, the High Efficiency Video Coding (HEVC), at the cost of increased complexity. Hence, to meet real-time and energy efficiency requirements, portable devices must adopt techniques to effectively reduce the VVC complexity, including customized hardware accelerators. This work presents a low-energy hardware architecture design for the Fractional Motion Estimation (FME), which is amongst the most critical VVC and HEVC encoder steps. The proposed architecture reduces the FME complexity by operating over a subset of candidates selected to reduce the energy and area demands without compromising too much the coding efficiency. At the average BD-Rate of only 0.34% and 0.28% for the Low Delay with P slices only (LD-P) and Random Access (RA) configurations, respectively, the proposed architecture achieves a 75.5% energy consumption reduction when compared to a baseline FME architecture while occupying only 36.6 % of the area.