Substrate Bias Effect of 28 nm-node HK/MG nMOSFETs with DPN Temperature Treatments

As the substrate bias is applied and increased, the V$\tau-$value for the tested device is generally raised up. The channel concentration for the lower-annealing group is regularly decreased with the geometric sizes of tested devices shrunk. However, this phenomenon is not observed well for the highannealing group. The repair of oxide trap in high-k gate dielectric with the higher annealing temperature is indeed better than that with the lower one, reflecting the higher drive current and the lower V$\tau-$values, but the device size narrowed down produces an extra disturbance in the yield control.