Improved Self-Biased Differential Amplifiers Using Multiple-Vt CMOS Transistors

This paper analyzes several self-biased topologies to implement differential amplifiers with single-ended output. Self-biased circuits potentially save area and power since they do not need dedicated current sources and mirrors. Moreover, the design is simplified because the circuit remains in the operating region independently from the transistor dimensions. These advantages come at the cost of larger sensitivity of the consumed current to process variations, this fact must be considered during design. The studied configurations are improved by using multiple-Vt (threshold voltage) transistors, which are available in conventional CMOS processes. One of the topologies is used to design an output buffer aiming to measure a rail-to-rail analog signal. The buffer is simulated in a CMOS 65nm technology and consumes 235μW with a 23MHz bandwidth in typical case. The fast and slow corner models are also accounted, resulting in worst case variations of up to 37% in power consumption. The methodology proposed shows how self-biasing can facilitate circuit design.