FlexGen: An Adaptive Pipeline Generator for Programmable Data Planes

In recent years, the programmability of data planes has been extensively investigated. However, users still face challenges in conveniently expressing their data plane algorithms due to the tight coupling between compiler back-ends and chip-specific architectures on data planes. Even Lyra, a compiler that allows programmers to achieve portability, extensibility, and composition in data plane programming, does not support mapping instructions for additional capabilities, such as computing, storage, and security, in intermediate representations to P4 or NPL. In this paper, we introduce FlexGen, a flexible pipeline generator that generates configurable or executable code for multiple heterogeneous targets, incorporating additional platform capabilities such as computing, storage, and security on data planes. We compile benchmarks from real production networks to three different programmable switch architectures, and our experiments demonstrate that FlexGen generated code runs at line-rate across all packet sizes, achieving latencies comparable to those of commercial ASICs.