Failure Analysis Methodology on Solder Bump Bridging Defects for 14nm Technology

Semiconductor industry has been putting tremendous efforts on 2.5 D technology in accordance with the increasing demand for better capacity and system performance. This technology enables several silicons to communicate up to the speed of Gigabits per second while reducing the cost for a system with heterogeneous components. However, such new technology also poses great challenges whereby the manufacturing of this interconnect structure is a complicated and defect-prone process. The most common failure that happened is so called solder bump bridging issue [1]. In this paper, will mainly discussed about the SBB (Solder bump bridging) whereby it is a type of package defects involved with two or more adjacent solder bumps that mainly located at C4 interconnect layer (C4, is a method for interconnecting dies such as semiconductor devices, IC chips, integrated passive devices and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads, between flip chip die and substrate) [2]. Majority of SBB defects resulted in EIPD (Electrically Induced Physical Defects) failure from customer returns known as FACR (Failure Analysis Customer Return) from field failure. Electrical failure analysis found common failing symptoms on suspected SBB units such as specific failing subtests, pin resistance comparison. Physical failure analysis root cause the affected SBB were found on unused AIB (Advanced Interface Bus).

I. Introduction

Alongside the process node advancements, Intel also must march forward with next-generation packaging technology. The demand for high performance silicon coupled with increasingly difficult process node development has created an environment where processors are no longer a single piece of silicon, relying on multiple smaller (and potentially optimized) chip lets or tiles to be packaged together in a way that benefits performance, power, and the product. By having EMIB (Embedded Multi-Die Interconnect Bridge) technology, Intel uses a small slice of silicon and embeds that directly into the substrate through package vias. This is calling a bridge. The presence of bridge is effectively two halves with hundreds or thousands of connections each side, and the chips are built to connect to one half of the bridge. Now both chips are connected to that bridge, having the benefit of transferring data through silicon without the restrictions [3].