Power and Delay Analysis of a CMOS Inverter

The major challenge in designing and synthesizing VLSI circuits is to minimize propagation delay and Power Dissipation (P
d
). This depends on the design parameters such as W/L ratio, scaling technology, and load capacitance. This paper focuses on detailed study of the propagation delay and dynamic power of a Complementary Metal Oxide Semiconductor (CMOS) inverter considering a channel length below 45nm following which, the best geometry for the minimum delay is found. For simulations, the standards of model parameters are used from the Berkeley Predictive Technology Model (PTM), and the study is performed for the technology including 16nm, 22nm, 32nm, 45nm with the help of the Electric software and LT Spice simulation tool. Our study shows that the CMOS inverter designed using the proposed methodology enhances the static and total power dissipation in comparison to the conventional design. The results demonstrate that a variation of the load capacitance leads to a change in the delay and dynamic power, and the technology scaling results in an increase of delay; however, with a decrease in the dynamic power values.