Design and Implementation of an Adder Circuit for Minimal Power and Less Delay Systems

This work represents full adder proposed using Pass Transistor Logic. A complete adder's performance is determined by its consumption of power and delay. Power consumption and delay are important design factors for contemporary digital circuits, and a lot of study has been devoted to optimizing these factors. A comprehensive adder circuit is implemented utilizing Pass Transistor logic. In this circuit, 10 transistors are utilized. The effectiveness of a complete adder system to operate under minimal power and delay conditions. has been enhanced in this paper, using Cadence Virtuoso Computer Aided Design (CAD) software on 90 nm process node. By examining the PDP, power usage, and delay the effectiveness of the suggested circuit design is evaluated.