A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node

The standard cells are becoming increasingly smaller due to aggressive device down-scaling, and power rails take up a sizable portion of the available space. Buried Power Rail (BPR) and Back-Side Power (BSP) have been gaining more attention owing to their capacity to reduce the standard cell height from 6-Track in the traditional Front Side Power Rail (FS-PR) to 5-Track and 4-Track, respectively. In this paper, we provide a comprehensive comparison of power rail topologies at the device, standard cell, and full chip design level in terms of Power, Performance and Area (PPA). Our experiments show that nanosheet width scaling for BPR and BSP reduces device gate capacitance by 26% and 40%, respectively, resulting in an improvement of internal power of over 33% and 40%, respectively, at the standard cell level, and total power drop of over 24% and 30%, respectively, at the full chip level. Additionally, the floorplan can be shrunk down by 7% with BPR compared to FSPR, and even further by an additional 17% with BSP. This study also demonstrates the Back-side Power delivery network (BS-PDN) benefits in IR drop for BPR and BSP topologies.