Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators

Resistive Crossbar (Xbar) Array based Compute-in-Memory (CiM) accelerators form an attractive hardware substrate for acceleration of Deep Neural Networks (DNNs) on edge devices. They perform highly efficient Matrix Vector Multiplication (MVM) operation, employing the power of analog compute. However, efficiency gains with CiM accelerators are limited due to the overhead posed by peripheral circuits, primarily the Analog-to-Digital Converters (ADCs). In this work, we improve efficiency of CiM accelerators by developing ADC-Less and near ADC-Less CiM accelerators which either eliminate or minimize the ADC overhead. More specifically, we leverage partial-sum quantization to reduce ADC precision to binary (1-bit) or ternary (1.5-bit) values. Xbars with binary partial sums require a sense amplifier for analog-to-digital conversion leading to ADC-Less design. Xbars with ternary partial-sums require two comparators for the conversion process leading to a near ADC-Less design. We develop a CiM hardware aware DNN quantization methodology to mitigate accuracy degradation with partial-sum quantization. We show the effectiveness of our training methodology by achieving high accuracies and minimal accuracy degradation on CIFAR-10 and Imagenet datasets. Consequently, we achieve 14x, 178x and 131x improvements over baseline (8-bit ADC) in Energy, Latency and Compute Efficiency (TOPS/mm
²
), respectively on Resnet-20 (CIFAR-10) with ADC-Less design and 11x, 55x and 36x improvements over baseline (8-bit ADC) in Energy, Latency and TOPS/mm
²
, respectively on Resnet-18 (ImageNet) with Near ADC-Less design.