High Spectral Purity Clock for High Speed ADC and DAC

In this paper describes the generation of high spectral purity clock for high speed ADC and DAC. ADC and DAC requires low jitter clock is essential to achieve high performance. 500MHz and 1000MHz clocks required for ADC and DAC respectively and also derived from high stable OCXO 125MHz reference signal by using two frequency multipliers (X2 and X4). Based on the clock requirements, an architecture and implementation finalised. Finally, the fabricated prototype was measured. The maximum sampling clock of ADC is 1.3ns and RMS jitter is 0.2ps and for ADC and DAC provides, 12-bit resolution, 3 Gsps Guaranteed Conversion Rate and master clock to DSP is 1.6ns. BPF is selected for wide stopband rejection at 1GHz and 500MHz, and LPF is utilised in the following step to offer rejection greater than 40 dB, output level to the DAC is 5dBm and for ADC is 0dBm.