SI/PI Co-Design of 12.8 Gbps HBM I/O Interface using Bayesian Optimization for PSIJ Reduction

In this paper, we propose SI/PI co-design method using Bayesian optimization (BO) for power supply noise induced jitter (PSIJ) reduction in 12.8 Gbps high bandwidth memory (HBM) I/O interface. PSIJ is becoming significant SI/PI problem as the operating speed increased, in particular HBM with huge I/O counts. SI/PI co-design is needed for accurate PSIJ prediction since it is determined according to the not only power domain such as power distribution network (PDN) and jitter sensitivity of circuit, but also channel loss. First, PSIJ is modeled analytically. Each target design parameters are RLC circuit components of interposer and on-chip for PDN, circuit delay of I/O driver for jitter sensitivity, and physical dimensions of interposer for channel. Then, these eleven design parameters are optimized in the continuous space based on PSIJ value using BO. As a result, SI/PI co-design is effectively performed through PSIJ-based BO, and the system-level trend of each I/O interface component can also be analyzed. Also, the proposed method based on BO is verified to outperform compared to random search (RS) algorithm.