Comprehensive Optimization of Differential Via Design for High-Speed Applications

The significance of signal integrity is increasingly paramount, as there exists a strong imperative to ensure high-quality signals in all components, including the smallest elements such as via design. Generally, via design on a printed circuit board (PCB) does not hold a substantial role until data rates reach 10 Gbps and beyond, especially with respect to PCIe Gen5 and Gen6, where the Nyquist frequency attains 16 GHz. To minimize undesirable noise and maintain signal integrity, it is highly critical to design via impedance and loss. In this study, we explore the impacts of drilled hole size, pad size, anti-pad size, via pitch, via length, and stub on via designs. A comprehensive optimization of each parameter is performed to evaluate the dominant effects.