Efficient Accelerator Design in High-Level Synthesis Using Approximate Logic Components

FPGA-based architectures have emerged as a versatile acceleration solution for various applications, aided by High-Level Synthesis (HLS) tools. For applications with some level of error resilience, the use of approximate logic components such as imprecise multipliers and adders can improve resource usage and energy efficiency. Nevertheless, these components must be carefully composed and combined to prevent error accumulation and to ensure that the application produces valid outputs. In this work, we explore approximate multiplier and adder designs used in Multiply-accumulate (MAC) operations for accelerators implemented in HLS, aiming to find combinations of components that can save power and resources while effectively mitigating errors in application outputs. We show that the best combinations of components can improve the Power Area Product (PAP) of a Sobel filter accelerator design by 36-49% compared to a precise design while limiting errors and maintaining an acceptable quality of results.