A Novel Test Data Compaction Method with Improved Debug Capabilities of the Signatures

Built- In Self Test (BIST) is mandatory in current day automotive ICs and widely adopts space and time compaction methods like Multiple Input Signature Registers (MISRs). The BIST methods are primarily used during in-field testing to identify only pass/fail without much focus on debug/diagnostics due to compaction of large number of bits. In this paper, we have introduced a novel space and time compaction scheme which identifies the exact location of fault capturing scan cells using simple signature analysis based on elementary mathematics, improving the debug capabilities. Along with the mathematical proofs, we also demonstrate the added advantages of this scheme in terms of scalability, ability to adopt existing top-off on-chip signature comparison methods which makes it flexible to be used in both manufacturing and in-field testing. The validation process of the proposed idea have also been discussed, including the results wherein for every simulation, we obtain 100 % accuracy. The hardware implementation options have also been discussed briefly.