MBIST-HSIO Concurrent Testing Strategies and Test Challenges

Semiconductor chips are getting complicated with increasing transistor density onto the same
$mm^{2}$
area. As the complexity of chips increases, test cost surges since it holds a significantly larger part on the Silicon design process. Test-Time is one of the key parameters which decides per chip test cost. The methodology proposed in this paper helps to reduce the test cost significantly. This paper focusses on the strategies defined by the authors to enable concurrent testing between two major testing blocks HSIO and MBIST. Both the blocks have a lot of variation on vector structure and way in which they are tested. The paper discusses the challenges that authors have faced during implementation and silicon bring-up. Finally, the paper highlights the savings that's been seen across designs where this approach has been implemented.