A Novel Approach for Dynamic Power Reduction in SRAM Cache Memory Bit-Cell at Deep Sub-Micron CMOS Technology

Today, considering our online presence on social media (e.g., Facebook, Instagram, WhatsApp, Bigo, etc.), online gaming, online shopping, online data processing, real-time search, implementation of AI and ML algorithms etc., we are generating and processing trillions of bits of data every single moment. As per various sources, the use of social media and online data processing will increase in future at an alarming rate. Therefore, to handle this huge amount of data and data processing, we need powerful processors (both CPU and GPU). Therefore, the high speed and large size L1, L2, and L3 cache memory with a critical need for static and dynamic power as a threatening consideration especially for battery powered electronic gadgets, mobile phones, tablets, laptops, smart watches, and invasive/non-invasive medical devices, etc. is needed. On-die/embedded memory is sufficient to address the growing need for low-power and higher performance Systems-on-Chips (SoCs). Due to concerns with leaking power, performance, data retention, and stability in lower technological nodes, Deep-Sub-Micron (DSM) technology, i.e., 90nm or lower, is facing a threatening challenge. In this work, a novel extremely low-power and low-stress SRAM bit-cell, called Asymmetric Improved P3 (AIP3) SRAM bit-cell has been proposed as an integrated cell in the cache memory to optimize the dynamic power consumption. This bit-cell offers a unique and asymmetric data handling capability due to its separate data read, write, and hold sub-circuits in the data read/write circuits. The projected AIP3 SRAM bit-cell has shown a substantial reduction in the dynamic write and read powers in comparison to the conventional 6T and IP3 bit-cells. The proposed bit-cell has been designed and verified at VDD=0.9V, Vth=0.68191V, tox=1.2e-9, xj=5e-9 and at 16nm PTM Low-Power CMOS Technology.