Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge

With the emergence of FPGA boards equipped with high bandwidth memory (HBM), these boards have become more attractive for implementing memory-intensive computational kernels such as sparse matrix-vector multiplication (SpMV), with a wide range of applications in edge computations from deep learning to robotics. Specialized implementation of SpMV on FPGAs enables efficient utilization of the limited resources in edge systems. High-level synthesis (HLS) compilers, on the other hand, have eased the programming of FPGAs, leading to a faster development cycle. Even though the programming of FPGAs has become easier, obtaining maximum throughput even for the straightforward kernel of SpMV still requires careful optimizations. Therefore, this paper explores the impact of deploying various optimization techniques such as temporal parallelism, spatial parallelism, and memory alignment to help SpMV fully utilize the available memory bandwidth of HBM on a Xilinx FPGA board to achieve close-to-peak throughput without wasting the resources. We conclude the optimizations by suggesting Spica, a high-throughput tree-based SpMV implementation.