Novel Ferro-Oxide-Nitride-Oxide-Semiconductor (FONOS) FDSOI FET Towards Memory and Synaptic Applications

In this work, a charge trapping nitride (CTN) assisted memory window (MW) boosting by a novel ferroelectric-oxide-nitride-oxide-semiconductor (FONOS) based memory FET is investigated. The proposed architecture is obtained by a calibrated state-of-art Si: HfO
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FDSOI FeFET TCAD numerical simulations. The calibrated FeFET is further added with charge-trapping-memory and tunnelling models to incorporate the effect of adding a charge-trapping-nitride layer between ferro-electric and silicon layer to form the proposed FONOS FET. The FONOS device has predicted low program/erase (PGM/ERS) biases of + 4.5 V and −5.0 V, which is predicted to be enhanced by Fe layer. The physical insights into this phenomenon are thoroughly predicted in the positive and negative hysteresis loops of Fe layer that traps/de-traps the electrons and hole in the Si
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layer. A brief schematic and array structure to use the proposed FONOS device is provided to further extend the work towards applications on neuromorphic computing.