Design and Analysis of Imprecise 4-2 Compressor with Error Recovery Module for Approximate Multipliers

As an effective method to improve chip energy efficiency, approximate computing has been widely concerned and studied by industry and academia. In this paper, we present a novel approximate 4-2 compressor. In addition, we also made a comprehensive comparison of the approximate 4-2 compressors proposed in the literature. The investigated circuits are employed to design an 8×8 Dadda multiplier. The experimental results show that compared with the exact multiplier and other advanced multipliers, the proposed multiplier has improved the area, power consumption, and delay by 12%, 15%, and 14% respectively, and has significantly improved the ER and NMED by 21% and 58% respectively. The application of image multiplication is also introduced to evaluate the practicability of the multiplier through peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM). The experimental results show that the PSNR and MSSIM of this design are better than other designs.