Rapid FPGA implementation of a cost effective quaternion LMS estimator

In this paper, a rapid field-programmable gate array (FPGA) prototyping of a variable tap-length, cost-effective least mean square (LMS) algorithm applied in the quaternion space (QLMS) is investigated. The design method involves the description of the QLMS behaviour in C programming language and its hardware implementation, using VITIS high-level synthesis (HLS) tool. The approach proves to be highly effective in terms of achieving fast FPGA designs, high performance vs hardware resources used, and a low computational cost vs data throughput. Simulations and FPGA implementation reports of the adopted QLMS algorithm applied to real-world quaternion based 3-D orientation data confirm the superiority of the proposed approach over the original QLMS.