On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers

Voltage over-scaling (VoS) may be one of the most effective power reduction approaches, however, it makes circuits susceptible to timing failures. Various techniques were proposed to facilitate VoS by detecting and correcting errors and moving away from traditional voltage and timing guardbands. However, such approaches require the addition of extra redundant hardware leading to area and power overheads, especially in case of large timing errors. Recent, complementary approaches tried to redesign the target circuits, however, they were not yet applied on complex pipelined architectures like floating point multiplier which is extensively used in neural networks and other popular applications. In this paper, we develop a low-power pipelined floating-point IEEE-754 compatible multiplier that can operate reliably under voltage over-scaling (VoS). This is achieved by applying a path-shaping approach that helps minimize the number of paths susceptible to timing errors under lower voltages. In addition, our micro-architectural modifications isolate the critical paths only to a single pipeline stage, thus minimizing the error-prone stages under VoS. To showcase the efficacy of our approach, we perform post-place dynamic timing analysis using various benchmarks, indicating that our design can lead up to 171% better SNR, 80% less BER and 36% less power under 18% less voltage compared to the baseline multiplier. The applied analysis reveals that our approach can help limit the erroneous outputs of the unit by up to 74% and reduce by 20% the multi-bit error probability, in such a widely used arithmetic unit.