A Low-Power SAR ADC with Multi-mode Switching Scheme

This paper proposes an energy-efficient switching scheme for successive approximation register analog-to-digital converter (SAR ADC). This switching scheme adopts constraint bit control and asynchronous SAR logic to reduce the area and power consumption of ADC. The combination of top-plate sampling, monotonic switching and multiple reference voltages prevents the capacitor array from generating dynamic power consumption in the first three comparison stages. In the subsequent comparison stages, the difference of bottom-plate voltage switching under the corresponding weight-bit capacitance is only 1/4$V_{\mathrm{ref}}$. Compared with the conventional scheme, the proposed scheme saves 99.61% of the average dynamic power consumption and reduces the total capacitance by 87.5%. An asynchronous 8-bit SAR ADC based on the proposed scheme is implemented in a 65 nm CMOS technology. At 1.2 V power supply voltage and 5 MS/s input sampling rate, the power consumption of SAR ADC is 25 μW and the FOM is 22.1 fJ/Conv.