Integration And HCI Improvement In Deep Sub-Micro CMOS process

CMOS Enhanced (CE) process derived from Logic process, The LDD implant of the I/O devices is merged into the S/D implantation. The advantage of this process is that it saves the 2 LDD Masks, While the disadvantage is the deep S/D implanting will deteriorate the performance of the core devices, and the I/O devices have high HCI reliability failure risk due to without targeted LDD. In the paper, the offset spacer (OFS) structure is implemented into 0.11um CE process to improve the HCI capability. Based on simulation and split experiment, the process conditions that can effectively reduce the performance loss of the core devices are obtained, also the effects of OFS process on devices are analyzed. Use the new process condition, the HCI capability can be greatly improved, and the performance of the core devices can meet the technical application requirement.