Closed-Loop Split-Phase Control Applied to the Symmetric Dual Inductor Hybrid (SDIH) Converter

Hybrid switched capacitor converter (HSCC) topologies have found use in high-density power delivery applications, such as 48 V to Point-of-Load (PoL). Of this family, Dickson-type converters are recognized as having the lowest Volt-Amp switch stress, indicative of a smaller semiconductor footprint for equivalent performance. However, some of these topologies require a nonconventional clocking scheme – termed “split-phase” switching – to ensure that capacitor-induced hard-charging losses are avoided. A small number of recent works have analyzed split-phase switching with varying degrees of rigor, however, to date no closed-loop active control scheme has been demonstrated. This work presents a hardware implementation of closed-loop split-phase control, eliminating both hard-charging losses and reliance on modelled converter operating points, while providing an increased degree of immunity to component mismatch. Capitalizing on periodic low-noise switching states in which flying capacitors are inactive, a low-cost and high accuracy analog front-end is used to converge on optimal split-phase timing durations while maintaining output voltage regulation, irrespective of load.