The Study On Reducing Bit-Line Parasitic Capacitance In Advanced DRAM

In this paper, 3D TCAD (Technology Computer Aided Design) process and device simulation methods are used to explore the relationship between CBL (parasitic capacitance of bit line) and structure. The results show that BL spacer thickness and material property are critical to CBL. We suggest that BL profile should be vertical, which can give more room to BL spacer, then CBL will be reduced. Through process simulation, when BL TB ratio (top CD: bottom CD) increase from 0.6 to 0.9, the thickness of BL spacer increases by 1nm, and CBL decreases by 2. 7aF/cell.