Study On the Mechamism of SIN Residue FOR ILD0CMP

In the gate-last scheme, inter-layer dielectric level zero (ILD0) chemical mechanical polishing (CMP) for replacing metal gate (RMG) application has been developed to meet the criteria of high-k metal gate (HKMG) devices at 28nm technology node. The gate height uniformity, loading and dishing performance control are important process challenges. However, the opening of poly-Si gate is the principal factor in the construction of HKMG. Moreover, it’s a single-plank bridge that dummy poly-Si can be removed to deposit work function and aluminum metal. Long-term data shows the window of ILD0 CMP silicon nitride (SIN) residue is very narrow due to it’s too hard for CMP to cover pre-layers loading, such as STI dishing, step height, photo resist etch back (PREB) SIN horn, NMOS and PMOS (N/P) loading, oxide deposition thickness (THK) loading. In this paper, the inducement of SIN residue was analyzed and discussed in detail, which will supply inspiration for resolve this system issue.