Incremental Verilog Parser

Traditional hardware language parsers typically employ full-file compilation, which requires the entire file to be re-parsed even for minor modifications to the design code. This can result in long re-compilation times, particularly for industrial-grade chip designs that may have millions or even tens of millions of lines of code. This paper introduces an incremental syntax analysis technique for hardware languages and presents an incremental Verilog parser, Stagira 1.1, that utilizes this technique. Stagira 1.1 performs syntax analysis at the module level, determines the dependency relationships between modules based on module instantiation statements, and stores the abstract syntax tree structure and dependency table in binary files. The dependency table allows the user to recompile only the specified module and its related modules upon code changes, significantly reducing re-compilation times and enhancing the efficiency of chip development. The development of incremental parsers like Stagira 1.1 provides a solid foundation for the creation of various incremental EDA tools, which are essential for efficient hardware language parsing.