A Hierarchical Clock Network Synthesis Method for 3D Integrated Circuits with Obstacle Avoidance

As the technology node shrinks, the power consumption becomes a bottleneck for higher integration density. In the past decade, 3D integration technology is proposed to attack “power wall” and “memory wall”. Since clock distribution network consumes a large portion of the total power budget due to its high switching activity, the clock network design for 3D ICs attracts significant attention from both academia and industry. However, most works focus on the flat 3D clock network design which may not be optimal from the power consumption perspective. In this paper, we propose a hierarchical clock distribution network design, taking the general H- Tree structure as the global clock network, and the commonly used binary tree structure as the local clock network. In order to reduce clock skew and slew rate of the hierarchical clock network, we propose a co-optimization technique for TSV and clock buffer insertion. A skew re-balance technique is also proposed to reduce the clock skew when integrating the global clock network and the local one. Moreover, the hierarchical clock network design is enhanced with obstacle avoidance capability to facilitate the complex SoC design. Experimental results show that compared to the commonly used 3D clock tree synthesis algorithm, our hierarchical clock network can reduce power consumption and phase delay by 9% ~ 21% and 6.8% ~ 11.80% with the comparable clock skew and slew rate constraints.