A Statistical Evaluation Method to Quantify the Runtime Uncertainty of Accelerator-rich SoC Targeting EDA Acceleration

Integrating a host CPU with domain-specific accelerators is a promising way to improve the performance/power/area of EDA acceleration in the post-Moore age. But it is hard to estimate the runtime performance of the accelerator-rich SoC in the early stage, especially considering the uncertainty produced by PVT variation. To predict and further avoid the architectural risk, we propose a statistical model to evaluate the runtime distribution while targeting EDA acceleration. We first collect the dataset by the Latin hypercube sampling method and dump the output runtime data via gem5-SALAM simulator. After transforming the original dataset into the Gauss distribution through box-cox transformation, we integrate the least square boosting regression to achieve the deterministic estimation. Then we inject the uncertainties of frequency and unit yield, and thus the predictions become distributions. Based on the statistical evaluation method with a 4.3% normalized MSE, we can find that the experimental performance is usually worse than the original deterministic estimation, which proves the architectural risk.