A Learning-Based Method for Gate Delay Prediction under NBTI and Process Variation Effects

As the transistor process technology shrinks to nanoscale, aging and process variation effects become dominant issues affecting the chip reliability. Analytical evaluation at the early stages of chip design is critical to ensure that the chip will function correctly throughout its entire life cycle. In this paper, a machine learning model named Gaussian Process Regression (GPR) is proposed for predicting gate delay, which considers aging and process variation effects jointly. The experiment uses commercial 28 nm technology to simulate typical types of logic gates and verify the performance of GPR. Our approach can obtain accurate prediction with rRMSE score of 0.19% and MAE score of 0.14%, and significant runtime speed-up with 1000X speedup, with minimal loss of accuracy compared to the golden data.