On Accelerating PyRTL Simulation with Essential Signal Simulation Techniques

Agile hardware design method pursues rapid updating iteration of hardware design, and simulation, as an important guarantee for the correctness and effectiveness of design, is a crucial link in design iteration. The low speed of simulation limits the iterative speed, and accelerating the simulation can significantly accelerate the new iteration of design. Essential signal simulation (ESS) techniques accelerate cycle-based simulation by reducing the calculation of low activity factor signals. ESS has been successfully applied in several simulators, and achieved remarkable accelerations. In this paper we present our work on the implementation of ESS techniques on PyRTL. Compared with the PyRTL native-implemented CompileSimulation method, the new simulator generated with ESS enhancements can achieve up to 18.12% – 71.35% simulation cost reduction, and 12.97x – 108.35 x acceleration in simulation time.