A Variation-Aware Lagrangian Relaxation-Based Gate Sizing Framework for Timing Optimization

State-of-the-art work in academia on discrete gate sizing using Lagrangian relaxation (LR) has implemented the best leakage power reduction for runtime acceleration. In this paper, a new objective function is constructed by considering the gate-level delay variation to adapt to the optimization requirements of near-threshold circuits. We optimize the power consumption of the circuit while avoiding the deterioration of the worst delay of the critical path of the circuit. Based on the TSMC 28nm HPC Plus CMOS process at near-threshold voltage, the ISCAS89 test circuit is used for verification and comparative analysis. The validation results show that the proposed gate sizing optimization method can reduce the 3φ delay of critical paths by at least 5.63% on average compared to the state-of-the-art cell sizing method without introducing additional circuit power consumption.