Application Accelerated Verification In Embedded System

In this paper, we apply the digital twin verification to the aviation field, use the simulator as an important means of quantitative analysis of the architecture to guide the embedded system architecture design and application deployment, and propose a method to solve the slow simulation speed - sampling technology. We identify source code level programs as possible checkpoints, which are clustered by the basic building blocks of the program. During simulation, we only focused on these representative areas, loaded the simulator library and configuration of the microarchitecture being simulated, and fully warmed up the state of the microarchitecture, achieving 2467× of the average speed and 12% of the average IPC error. The experimental results show that sampling can significantly improve the simulation performance within the acceptable error range.