A Simple Gate Driver Design for SiC MOSFET Paralleled Operation

Paralleling operation of SiC MOSFET is one of the essential solutions to improve current rating of SiC MOSFET applications. In this paper, a simple gate driver design is proposed for SiC MOSFET paralleled operations. The driving delay time and voltage level of on-state can be adjusted flexibly without any usage of digital processors; hence it is more cost-effective and reliable for complex EMI environment of high voltage and frequency applications. The operating principle to alleviate the current error of paralleled SiC MOSFETs is described and analyzed. The performance of the proposed gate driver is verified by the experiment.