Comparative Analysis and Evaluation of Gate Driver Topologies for Paralleling Silicon Carbide (SiC) Power Modules

Paralleling SiC power modules is usually used to increase the limited current capability of SiC devices. Under very fast switching speeds (<100ns) of SiC MOSFETs, how to select the gate driver topology which effect dynamic current balance is very important. At present, the gate driver topologies for high-power paralleled SiC modules still follow the existing schemes for silicon counterparts, such as the isolated gate driver (IGD) structure, the non-isolated gate driver direct push-pull (NIGD-DPP) structure, and the non-isolated gate driver indirect push-pull (NIGD-IPP) structure. However, little literature has systematically compared and evaluated the suitability of the above gate driver topologies for paralleling high-power high-speed SiC modules. Therefore, this article presents a symmetrical bus structure with three paralleled power modules (1200V, 300A each). On the basis of this bus structure, the above three passive gate driver topologies are analyzed and compared. Effective current sharing has been achieved for the three paralleled SiC power modules.